A variety of substantially planar electronic devices are known, and include side-gated transistors for example. In such a transistor, insulative features are typically formed to interrupt a single layer of active material (that is electrically or electronically active material, such as electrically conductive or semi-conductive material) to define a relatively narrow conductive channel of active material connecting a source region or terminal to a drain region or terminal, and also to define gate regions on either side of the conductive channel to which potentials can be applied to control the conductivity of the channel. Each gate region comprises a respective area or region of the layer of active material and which lies in the same plane as the conductive channel and the source and drain regions.
A variety of substantially planar electronic devices are disclosed in the following published patent applications of the current applicant, the contents of each of which are incorporated herein by reference: WO 02/086973 A2, WO 2006/008467 A1, and WO 2006/120414 A2. These planar electronic devices include diodes (exhibiting self-switching behaviour as a result of the asymmetrical arrangement of the insulative features with respect to the two terminals of the device), other self-switching devices (that is devices exhibiting a degree of self-switching behaviour as a result of the arrangement of the insulative features), side-gated transistors (including transistors with just a single side gate and transistors with a plurality of side gates such as two side gates on either side of the conductive channel), and logic gates (such as AND gates, NAND gates, OR gates, NOR gates, etc).
From these individual devices, it is desirable to construct electronic circuits or parts of electronic circuits comprising a plurality of such devices (defined in a common layer of active material) and interconnections between those devices and connections to voltage rails, supply rails, input/output rails, ground rails, etc. It is possible to provide some of the required interconnections in the common layer of active material itself. For example, the plurality of insulative features which define the various planar electronic devices may also define one or more connecting portions of active material, each of which provide an electrical connection between one region of the layer of active material (such as a terminal of one of the electronic devices) and another region (such as a terminal of another device, or a voltage rail). Clearly, however, in general it may not be possible to provide all of the electrical connections required to define an electronic circuit from the planar devices in the layer of active material itself, and it may be necessary to provide additional interconnections outside the layer of active material (i.e. outside the plane of the devices).
However, the field of forming electronic circuits from planar electronic devices is a relatively new one, and the state of the art contains little information applicable to the problem of how to form connections between co-planar electronic devices other than in the same plane. A wide variety of techniques are known for producing electrical connections in conventional multi-layer semiconductor devices, but these are typically not directly applicable to the field of planar electronic devices, which typically utilise different materials and have different constraints associated with them. For example, numerous known techniques for forming interconnect structures from copper in multi-layer semiconductor structures incorporate features specifically adapted to address the problem of preventing contamination of the conventional semiconductor material by copper ions, which would at least degrade performance. Furthermore, in some of these known techniques for producing copper interconnects in multi-level semiconductor structures, arrays of trenches and vias are often overfilled with copper and it is then necessary to remove much of this copper, in an additional process step, to leave behind just the pattern of trenches and inter-layer vias.
To reiterate, conventional interconnect techniques are typically addressing very different problems from those associated with the formation of electrical circuits from a plurality of co-planar electronic devices and those known techniques are therefore typically not applicable in the field of the present invention.